Imec has strengthened its alliance with Vertical Compute while simultaneously unveiling a silicon interposer reference platform, positioning itself at the center of Europe’s race to overcome AI memory bottlenecks and advance chip packaging.
The Belgian R&D hub announced that Vertical Compute, a European startup founded in 2024, will deepen its collaboration with Imec to fast-track commercialization of its vertically integrated memory architecture. Vertical Compute’s technology, called Vertically Integrated Memory or VIM, places high-density magnetic memory directly on top of compute logic silicon.
Today’s AI processors burn energy and lose time shuttling data between separate memory and processing chips. Vertical Compute aims to shrink that data path from centimeters to tens of nanometers within one manufacturing flow. Data would sit locally, right where computation occurs.
The expanded partnership will validate Vertical Compute’s test chip at the 40nm node. It also sets the stage for producing a first pre-production 16nm product. A commercial foundry will handle the 16nm fabrication, while Imec adds the proprietary VIM layer using its NanoIC pilot line capabilities.
Meanwhile, Imec delivered baseline flows for its silicon interposer platform under the NanoIC initiative, a European Union-funded pilot line hosted by Imec. The platform documents architecture, manufacturing flow, and key design features, including through-silicon vias, multiple metal routing layers, and microbump pitches down to 20µm. Those specs enable dense connectivity between chiplets, memory, and specialized dies in 2.5D packaging.
Process design kits for the silicon interposer should arrive in early 2027. Universities, startups, and fabless chip firms can then design with the technology using industry-standard EDA tools from Cadence and Synopsys. The interposer represents one of three advanced interconnect technologies under NanoIC development, alongside fine-pitch RDL interposers and die-to-wafer hybrid bonding.
