EU launches NanoIC pilot line to oversee development of sub-2nm chips on the continent

EU launches NanoIC pilot line to oversee development of sub-2nm chips on the continent


The European Union (EU) has launched its largest Chips Act pilot line to date – a €2.5 billion ($3bn) facility dubbed NanoIC at Imec Leuven, in Belgium.

Dedicated to the development of advanced semiconductors, the EU and national and regional governments both invested €700 million ($834m) in the project, with the remainder of the funding provided by ASML and other indusattempt partners.

The facility was first announced in May 2024, with the opening of NanoIC following the inauguration of the FAMES pilot line on January 30. Houtilized at CEA-Leti in Grenoble, France, FAMES saw a total combined investment of €830m ($989m) from the EU and participating member states, and will focus on Fully Depleted Silicon-on-Insulator (FD-SOI), a manufacturing process that allows chips to operate at significantly lower voltages.

The NanoIC pilot line is hosted by R&D organization Imec, with support also coming from other research labs, including CEA-Leti, Fraunhofer of Germany, VTT of Finland, CSSNT of Romania, and the Tyndall Institute of Ireland.

In a statement, the European Commission has stated the NanoIC will be the first European facility to deploy the most advanced Extreme Ultraviolet (EUV) lithography machine, tools built by ASML, and necessary for the manufacturing of 2nm and sub-2nm semiconductors.

Researchers and chip companies will be able to utilize the facility to test new chip designs, equipment, and processes at a near-industrial scale before mass production, it added.

Five pilot lines – NanoIC, FAMES, APECS, WBG, and PIXEurope – are planned under the Chips Act, with the projects representing a combined EU and national investment of €3.7 billion.

Approved in April 2023, the €43 billion ($51bn) EU Chips Act was established with the intention of doubling the EU’s global market share in semiconductors from 10 percent to at least 20 percent by 2030. Originally set to focus only on high-finish chips, it has since expanded to include older chips and research and design facilities.



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